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I just spent a good part of the last week or so laying out the RFM69HW BreakoutBoard.  Whew!   I might have spent my youth differently If I had only known that unravelling a knotted up ball of yarn was an important skill in building a PCB.   I have been moving right along taking my idea of wanting an RFM69HW breakout board to PCB.  In the first post I created the schematic.  In the subsequent post I picked the parts and ordered them from digikey.  Now it is time to lay out the parts and draw the in kicad’s PCB layout tool – PCBnew.  

Updated schematics and board layout can be downloaded from the Bitknitting GitHub repository.

Thanks to Those that Go Before

THANK YOU to the exceptional folks that share their electronics knowledge.  I have a deep gratitude.

I hope every learner has the opportunity to tap into the people and knowledge that I have been able to tap into.  Each day brings in a new piece of knowledge about electronics or embedded systems that becomes a important in support of my passion to build stuff that brings me fresh tomatoes year round with minimum effort.  

It is always important for me to acknowledge the key contributors to a post.  For this post, a moment of gratitude goes to:

  • Chris Gammel - our very knowledgable and gifted instructor of Contextual Electronics.  A course I would highly recommend if you are interested in turning your prototypes into PCBs and learning tons about electronics along the way.  There is no way I would be able to get this far without Chris’s class and his recommendations/insights.
  • Felix Rusu (lowerpowerlab.com)has posted the schematic and board layout (also in Eagle) for the Moteino.  This is well worth a look (the github link to the Moteino schematic and board layout).  I downloaded the free copy of Eagle, got familiar with how to show and hide different layers, and stared at how Felix decided to layout the Moteino.
  • Martynj and Plutonomore from the jeelabs forums.  Both have been very willing to share their knowledge in this space – something both have a lot of!  Martynj spent time walking me through the basics of why the cc3000 and RFM69HW SPI bus is having trouble sharing the SPI bus as well as other insights.  Plutonomore created a RFM69HW Arduino Shield and posted his work.  A wonderful way for me to gain insight from a person who has gone before.

The Goal

The goal of this post is to layout the parts that I ordered on digikey onto a virtual representation of the RFM69HW breakout board.  The key things I will be doing include:

  • chip placement on the front and back of the PCB.
  • drawing traces to connect the chips – i.e.: the copper routes in the PCB that replace the jumper wires used on a breadboard.  
I will be using kicad’s PCBnew tool.  I will not be delving into how kicad works.  This video might help if you want to get an idea on the purpose and how the PCBnew tool works.

The Process

As in the previous post on associating parts to schematic symbols for the RFM69HW breakout board, I start with the net list.  After reading in the net list into PCBnew, the steps include:

  • another look at part selection.  Schematic -> PCB is a very iterative process.  Place parts and connect circuits.  Get feedback.  Think about.  Move around parts and traces or start over.  Repeat over and over until the layout “should work.”
  • defining the width and length of the board and drawing a board outline.
  • placing parts and drawing traces.  

Another Look at Part Selection

The Level Shifter

My increased knowledge of SPI  and the need to bridge a 5V (digital i/o pin) Arduiino Uno with a 3.3V IC (here is a nice explanation and proposed solution) – like the RFM69HW – got me rethinking the approach I took.  Until this look, I had decided on:

  • not addressing the MISO line.  This line (as MISO suggests – Master In, Slave Out) has the RFM69HW sending 1’s and 0’s to the Arduino Uno.  See this post for more details on sending 1’s and 0’s between 3.3V and 5V components.
  • using the 74LVC245 (data sheet) to level shift the MOSI, CS, and CLK lines from 5V signals to 3.3V signals.
I changed my mind.  I do want to address the MISO line.  I kept having the recurring thought that some of the circuits I plan to prototype will use the cc3000.  Recall from my post on creating the schematic where I reviewed the MISO line’s challenge, I included this comment from Adafruit support:

In practice, the CC3000 has a quirk: it doesn’t release the MISO line when the CS pin is HIGH. On the CC3000 Shield, we added a buffer chip that isolates the data lines correctly. The breakout doesn’t have a buffer, but you can add one externally.

While I’ve moved from using the breakout board to using the cc3000 shield, I decided to make the RFM69HW breakout board more robust.  The other benefit is I will most likely learn something new.  Which is one of the main reasons I am creating this breakout board in the first place.

The 74LVC245 – the Chip Leaves MISO Shiftless

The 74LVC245 can go from 5V -> 3.3V, but cannot shift from 3.3V -> 5V.  So I can’t use that chip.  I decided to replace the 74LVC245 with the a 74HCT level shifter.  I’ve chosen the 74HCT125 (data sheet).  This IC has 4 buffers, the perfect amount to handle the 4 SPI lines.

The updated pdf of the schematic with the 74HCT level shifter is located in the Bitknitting GitHub repository.

As noted in the general description within the  74HCT125 data sheet:

The 74HC125; 74HCT125 is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A HIGH on nOE causes the outputs to assume a high impedance OFF-state.

 
CSForVoltageRegulatorBuffer
My first pass connected  the CS line to a buffer’s OE pin.  This is because CS is LOW  when MOSI/MISO data is sent and received between the Arduino and the RFM69HW.  Chris recommended simplifying the layout by always having OE set to low. His recommendation made sense to me because I don’t expect the signal to get much noise.

Test Points

I assume there will be additional iterations on the PCB board.  So for my earliest fabrications, I will be putting in test points so that I can test the signals.  I decided to change these from through hole – where I solder on a piece of wire to attach a multimeter to – to a copper pad.  This means less soldering and no test wires dangling from the breakout board.

Define the Board Size

I took a stab at laying out the parts without drawing traces and will start with a 1″ x 1″ board.  I will be using OshPark for fabrication.  This is where Chris had us go to when I ordered my Getting To Blinky boards.

Considerations I used to determine the board size included:

  • fitting all parts and components on a 2 layer board.  I don’t see any reason to have more than 2 layers.
  • cost to fabricate the board(s).  The larger the board, the more it will cost me to make.

  The pricing info  comes from OshPark’s home page:

2 layer boards are $5 per square inch (with 3 copies of your board included in that price) and ship in under 12 calendar days from ordering. 
4 layer boards are $10 per square inch (also including 3 copies of your board), go to the fab once a week, and have a 2 week turn time from the fab.

This adds $1.67 / breakout board to the cost of goods.  In the previous post, I purchased 4 sets of parts.  Hopefully I will be able to solder 3 together.  I definitely will need to practice soldering since I have not soldered SMT packaged parts.  Luckily, we’ll soon be doing SMT soldering in the Contextual Electronics course I am taking.  I have also ordered SMT soldering practice boards.  In the upcoming weeks I will practice, practice, practice soldering SMT packaged parts – that look smaller than an ant – to practice boards.

Place Parts and Draw Traces

Placing parts and drawing traces reminds me of putting a puzzle together. It can be frustrating. it can be funIn the sort of way Mary Poppins sings in Disney’s Mary Poppins movie:

In every job that must be done there is an element of fun.  You find the fun and snap, the job’s a game…

The Ratsnest

My layout started with an appropriately named state –  a ratsnest:

ratsnest



First Pass at Layout

Here is my first pass:

 

 

PCBLayut

The red is the front of the board, the green is the back of the board.  The RFM69HW takes up a large portion of the front of the board.  The back of the board has the 74HCT125 and the MCP1703.  I also put the capacitors on the back.  It took me awhile to figure out non-crossing paths when the traces need to connect components that are mirroring each other.

 

After spending several days creating layouts, these things helped me get this far:

  • being able to analyze other works – like Felix Ruso’Moteino layout – gives perspective from folks that have “been there done that.”
  • error checking tools – ERC for the schematic and DRC for the layout – are great friends!  I benefited from Chris’s words of wisdom in the Contextual Electronics course.  I receive some errors from ERC that I chose to ignore.
  • running kicad’s autorouter tool gave me a reference layout.  Since it would be very difficult – if not impossible – for the auto routing tool to generate a final layout, I did find it useful to see where  it drew traces.  I did not evolve this the auto routed layout.  Rather, I stared at it a long time and used some of the trace paths it recommended.  It was a great way to see another view for unraveling the rats nest.

Chris reviewed the board and made many recommendations to improve the PCB layout:

  • Simplifying the layout by always having OE set to low.  My first pass connected  the CS line to a buffer’s OE pin.  The OE signal is LOW at the right time, because CS is LOW  when MOSI/MISO data is sent and received between the Arduino and the RFM69HW.   if you are not familiar with SPI bus traffic, perhaps this earlier post  on debugging the SPI bus will be useful.  
    Chris’s recommendation made sense to me because of the simplicity of the board. I don’t expect enough noise to add in setting the OE to low based on the signal from the CS line changed the routing in my second pass between the OE line of each buffer and GND.
  • Rotating the RFM69HW such that GND is in the upper left corner instead of lower right.  This puts the Antenna – an area that will most likely be more noisy – off in a corner.  I had also put the voltage regulator right next to the antenna – a particularly poor choice because of the noise that will come from the power signal.  Now the voltage regulator was as far as possible from the antenna.
  • Adding a copper pour region under the Antenna area to provide a ground plane for the antenna. 
  • Moving the decoupling capacitors for the RFM69HW to be closer to the RFM69HW’s 3.3V pin.  I changed the location in both the schematic as well as moved the capacitors (C4 and C5) closer to the 3.3V pin of the RFM69HW.
  • Do not use any VIAs near decoupling capacitors.  As Chris noted to me,  VIAs add inductance and worsen high frequency noise.  The circuit is best if there is the lowest inductance path to GND.Lowest inductance path to ground. That’s why want lower path.  Because the inductance acts like an open circuit, high frequency signals look like a short.  
  • I made an OOPS! error and placed R1 on the same layer and underneath the RFM69HW module.  I moved this down to the test point for the CS_5V and flipped.  This puts the pull up resistor (R1) as close as possible to the incoming CS signal.  Now there is a front trace (to the test pad) and back trace (to R1).
  • I switched which level shifter’s buffers were used by the MOSI, MISO, CLK, or CS lines used so that the result minimized cross-over routes.  I also switched the connector pins (P1), which helped a bit in minimizing cross-over routes.
  • I had made the VIAs too small.  Given OshPark’s design rules, the minimum VIA (outside) diameter must be 27 mils (13 mils for the hole (inside diameter) plus 2*7 mils for the annular ring.  I set the design rules for the VIA to have an outside diameter of 27 mils and an inside diameter of 13 mils.
OshParkViaSize
  • I used a track width of 10 mils.  OshPark’s design rules also note a minimum track with of 6 mils.  There is room to run wider tracks.  
  • I used a track width of 24 mils for +3.3V, +5V, and GND tracks .  For the VIA size, I used an outside diameter of 34 mils and an inside diameter of 24 mils.
  • Added a copper pour to the backside so that GND pads can access GND without having to draw traces.  This will help minimize the number of traces that need to be drawn and have  potential cross-over with other traces.o lower the number of nets.
I found this track width calculator to help me better understand what minimum track width is possible.  It turns out the track widths I chose are more than large enough.  Might as well leave them larger since there is room on the board to do so.
 

Second Pass at Layout

A Yippee! moment – my second pass at the layout after applying Chris’s recommendations and running ERC and DRC:
  

PCBLayoutRound2

Adding the copper pour for the GND net on the back (green) was a great help in lowering the number of tracks that needed to be routed since many pads were GND pads.

The copper pour GND net on the top (red) in the upper left corner (recommended by Chris) made a lot of sense once I understood a bit more on how planes work.   I do not want the GND circuit to connect to P12 TST (the hole for the antenna).  Doing so will short the board.  And it isn’t providing the “ground” mirror that the antenna would benefit from.   As it shown in the image, while the signal to GND travels to the GND pads, signal to GND DOES NOT travel to ANA (pad or hole for antenna).  

This is great!  Now there is copper helping out with the GND circuit and copper providing a ground for the antenna!

Thoughts on Learning Layout

I found these to be the most helpful in learning layout:

  • Chris’s Contextual Electronics course is an amazing opportunity to learn how to build a PCB.  I highly recommend it.
  • being able to analyze other works – like Felix Ruso’s Moteino layout – gives perspective from folks that have “been there done that.”
  • error checking tools – ERC for the schematic and DRC for the layout – are great friends!  I benefited from Chris’s words of wisdom in the Contextual Electronics course.  I receive some errors from ERC that I chose to ignore.
  • running kicad’s autorouter tool gave me a reference layout.  Since it would be very difficult – if not impossible – for the auto routing tool to generate a final layout, I did find it useful to see where  it drew traces.  I did not evolve this the auto routed layout.  Rather, I stared at it a long time and used some of the trace paths it recommended.  It was a great way to see another view for unraveling the rats nest.

Third Pass at Layout

Here I am – patting myself on my back and surprised that my arm doesn’t break from my enthusiastic patting….when I get an email from Chris.  He asked if I had watched the video on via stitching that he had made.  That is another amazing aspect of the Contextual Electronics course.  If we get stuck or could learn something that directly affects what we are designing, Chris will make a video on the subject, clearly explaining through example.  

Via stitching is a new term for me.  Here’s a definition I found on this post that made sense to me:

Via stitching is a technique used to tie together larger copper areas on different layers, in effect creating a strong vertical connection through the board structure, helping maintain a low impedance and short return loops.

Chris pointed out  I connect the two GND planes with a single trace.

PCBLayoutRound2AfterChrisReviewExplainVIAstitching

High frequency noise should flow through the GND as easy as possible to get back to its source.  If there is only a single trace to connect the top and bottom GND plane, there will be high inductance than if the GND planes are stitched together using vias.

The above image shows overlapping GND planes in the upper left corner of the PCB.  I stitched them together by “sewing on” vias.  A bit of BitKnitting!  Here is the updated PCB layout:

PCBLayoutRound3ViaStitching

Fourth Pass at Layout

While Chris was laying down test points for our Contextual Electronics project, he said something so obvious that in my excitement to finish the PCB layout I had completely forgotten.  A test point is just an exposed piece of copper where a probe can be inserted within a circuit.  Um…duh…this is how I was looking at SPI bus data all along!  I removed the test points near the connectors that allow access to the RFM69HW breakout board from the Arduino.  

That brings me to showing my fourth pass:

PCBLayoutRound4RemovedExposedTestPoints

Fifth Pass at Layout

Chris just showed us another thing we can do to improve our layouts that I wanted to share.  He noted pads 9, 10, and 11 had a lot of space around them that should be “tightened up” and the width of the spokes should be made smaller so that soldering would be easier.  In other words, he recommended adjustments to the thermal relief pads.  Thermal relief pads was another new term for me.  I found JYelton’s response on Stack Exchange to provide a very clear explanation of a thermal relief pad:

A thermal relief pad is essentially a pad which has fewer copper connections to a plane (such as a ground plane).

A normal pad would simply be connected in all directions, with the solder mask exposing the area to be soldered. However the copper plane then serves as a giant heatsink which can make soldering difficult, because it requires that you keep the iron on the pad longer and risk damaging the component…

Just to show a visual on normal vs thermal relief pads:

NormalVsThermalReliefPad

Normal vs Thermal Relief PCB Pad

The pad at left is connected to the copper plane (green) in all directions whereas the pad at right has had copper etched away such that only four “traces” connect it to the plane.

The goal then is to restrict the heat flow so that soldering onto pads 9,10, and 11 is easier.

Chris’s  recommendations include:

  • minimize the clearance
  • minimize the anti pad clearance
  • minimize the spoke/trace width between the pad and the copper pour
The two images show a “before” and “after” image.

* *

Fourth Pass

Fifth Pass

Another day, another opportunity to learn.  Today i learned that when there is a GND plane, I should evaluate the amount of space and the copper traces/spokes of thermal relief pads (and what the heck a thermal relief pad is)…

What’s Next

Please let me know how I can improve the layout.  My hope is by sharing I can help those folks that are new to this stuff and learn from folks that have done this.  There is so VERY MUCH I do not know/understand in this space!

The next step is to close on the PCB layout, get parts, and order boards from http://oshpark.com/.  

If I don’t get any feedback from you, I will close the PCB layout by checking the footprints I drew with the actual part.  If all is well – off to Oshpark for fabrication!  

Thanks for reading this far.  Please find many things to smile about.